STM32와 W5500 연결중에 멘붕.. IMR 및 RCR 이름이 중복됨.

최신 Wiznet 사의 W5500 칩을 테스트 하던중에 발견.

최신드라이버 파일이라고 잘 정리해 둔것을 보고 써보던중에 발견함.

 

uint8_t  getIMR(void)
{
   return WIZCHIP_READ(IMRw);  // 이렇게 수정함.
}

 

uint8_t  getIMR(void)
{
   return WIZCHIP_READ(IMRw);
}

 

#define IMRw               (_W5500_IO_BASE_ + (0x0016 << 8) + (WIZCHIP_CREG_BLOCK << 3))

 

RCR 도 마찬가지~

 

 

D:\test\Libraries\CMSIS\Core\CM3\stm32f10x.h 2861 #define  EXTI_IMR_MR10                       ((uint32_t)0x00000400)        /*!< Interrupt Mask on line 10 */
D:\test\Libraries\CMSIS\Core\CM3\stm32f10x.h 2862 #define  EXTI_IMR_MR11                       ((uint32_t)0x00000800)        /*!< Interrupt Mask on line 11 */
D:\test\Libraries\CMSIS\Core\CM3\stm32f10x.h 2863 #define  EXTI_IMR_MR12                       ((uint32_t)0x00001000)        /*!< Interrupt Mask on line 12 */
D:\test\Libraries\CMSIS\Core\CM3\stm32f10x.h 2864 #define  EXTI_IMR_MR13                       ((uint32_t)0x00002000)        /*!< Interrupt Mask on line 13 */
D:\test\Libraries\CMSIS\Core\CM3\stm32f10x.h 2865 #define  EXTI_IMR_MR14                       ((uint32_t)0x00004000)        /*!< Interrupt Mask on line 14 */
D:\test\Libraries\CMSIS\Core\CM3\stm32f10x.h 2866 #define  EXTI_IMR_MR15                       ((uint32_t)0x00008000)        /*!< Interrupt Mask on line 15 */
D:\test\Libraries\CMSIS\Core\CM3\stm32f10x.h 2867 #define  EXTI_IMR_MR16                       ((uint32_t)0x00010000)        /*!< Interrupt Mask on line 16 */
D:\test\Libraries\CMSIS\Core\CM3\stm32f10x.h 2868 #define  EXTI_IMR_MR17                       ((uint32_t)0x00020000)        /*!< Interrupt Mask on line 17 */
D:\test\Libraries\CMSIS\Core\CM3\stm32f10x.h 2869 #define  EXTI_IMR_MR18                       ((uint32_t)0x00040000)        /*!< Interrupt Mask on line 18 */
D:\test\Libraries\CMSIS\Core\CM3\stm32f10x.h 2870 #define  EXTI_IMR_MR19                       ((uint32_t)0x00080000)        /*!< Interrupt Mask on line 19 */
D:\test\Libraries\CMSIS\Core\CM3\stm32f10x.h 7511 #define ETH_MACIMR_TSTIM     ((uint32_t)0x00000200)  /* Time stamp trigger interrupt mask */
D:\test\Libraries\CMSIS\Core\CM3\stm32f10x.h 7512 #define ETH_MACIMR_PMTIM     ((uint32_t)0x00000008)  /* PMT interrupt mask */
D:\test\Libraries\CMSIS\Core\CM3\stm32f10x.h 7586 #define ETH_MMCRIMR_RGUFM    ((uint32_t)0x00020000)  /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */
D:\test\Libraries\CMSIS\Core\CM3\stm32f10x.h 7587 #define ETH_MMCRIMR_RFAEM    ((uint32_t)0x00000040)  /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */
D:\test\Libraries\CMSIS\Core\CM3\stm32f10x.h 7588 #define ETH_MMCRIMR_RFCEM    ((uint32_t)0x00000020)  /* Mask the interrupt when Rx crc error counter reaches half the maximum value */
D:\test\Libraries\CMSIS\Core\CM3\stm32f10x.h 7591 #define ETH_MMCTIMR_TGFM     ((uint32_t)0x00200000)  /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */
D:\test\Libraries\CMSIS\Core\CM3\stm32f10x.h 7592 #define ETH_MMCTIMR_TGFMSCM  ((uint32_t)0x00008000)  /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */
D:\test\Libraries\CMSIS\Core\CM3\stm32f10x.h 7593 #define ETH_MMCTIMR_TGFSCM   ((uint32_t)0x00004000)  /* Mask the interrupt when Tx good single col counter reaches half the maximum value */
D:\test\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_exti.c 86 EXTI->IMR = 0x00000000;
D:\test\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_exti.c 115 EXTI->IMR &= ~EXTI_InitStruct->EXTI_Line;
D:\test\Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_exti.c 230 enablestatus =  EXTI->IMR & EXTI_Line;
D:\test\Libraries\W5500_iolibrary_v100\ethernet\w5500\netctrl.c 82 setIMR((uint8_t)(option_value&0x00FF)); // set interrupt mask.
D:\test\Libraries\W5500_iolibrary_v100\ethernet\w5500\w5500.c 373 void     setIMR(uint8_t imr)
D:\test\Libraries\W5500_iolibrary_v100\ethernet\w5500\w5500.c 373 void     setIMR(uint8_t imr)
D:\test\Libraries\W5500_iolibrary_v100\ethernet\w5500\w5500.c 375 WIZCHIP_WRITE(IMR, imr);
D:\test\Libraries\W5500_iolibrary_v100\ethernet\w5500\w5500.c 375 WIZCHIP_WRITE(IMR, imr);
D:\test\Libraries\W5500_iolibrary_v100\ethernet\w5500\w5500.c 378 uint8_t  getIMR(void)
D:\test\Libraries\W5500_iolibrary_v100\ethernet\w5500\w5500.c 380 return WIZCHIP_READ(IMR);
D:\test\Libraries\W5500_iolibrary_v100\ethernet\w5500\w5500.c 393 void     setSIMR(uint8_t simr)
D:\test\Libraries\W5500_iolibrary_v100\ethernet\w5500\w5500.c 393 void     setSIMR(uint8_t simr)
D:\test\Libraries\W5500_iolibrary_v100\ethernet\w5500\w5500.c 395 WIZCHIP_WRITE(SIMR, simr);
D:\test\Libraries\W5500_iolibrary_v100\ethernet\w5500\w5500.c 395 WIZCHIP_WRITE(SIMR, simr);
D:\test\Libraries\W5500_iolibrary_v100\ethernet\w5500\w5500.c 398 uint8_t  getSIMR(void)
D:\test\Libraries\W5500_iolibrary_v100\ethernet\w5500\w5500.c 400 return WIZCHIP_READ(SIMR);
D:\test\Libraries\W5500_iolibrary_v100\ethernet\w5500\w5500.c 547 void     setSn_IMR(uint8_t sn, uint8_t imr)
D:\test\Libraries\W5500_iolibrary_v100\ethernet\w5500\w5500.c 547 void     setSn_IMR(uint8_t sn, uint8_t imr)
D:\test\Libraries\W5500_iolibrary_v100\ethernet\w5500\w5500.c 549 WIZCHIP_WRITE(Sn_IMR(sn), (imr & 0xF0));
D:\test\Libraries\W5500_iolibrary_v100\ethernet\w5500\w5500.c 549 WIZCHIP_WRITE(Sn_IMR(sn), (imr & 0xF0));